CPU Physical Design Timing Engineer

Qualcomm seeks a CPU Physical Design Timing Engineer to drive high-performance, low-power CPU implementations for next generation wireless and mobile SoCs. You will own timing closure for complex CPU blocks, performing constraint development, static timing analysis, ECO implementation, and sign off across multiple process corners. Partner closely with RTL, architecture, place and route, and PD teams to optimize performance, power, and area. Use industry EDA tools and advanced nodes to solve challenging timing issues. Contribute to methodology improvements, automation, and best practices in a fast paced, collaborative engineering culture.

Responsibilities

• Own timing closure for complex CPU blocks within advanced-node So
• Cs
• Develop and maintain timing constraints for synthesis and place-and-route
• Perform static timing analysis across multiple modes and corners
• Implement ECOs to fix setup, hold, and signal integrity issues
• Collaborate with RTL, architecture, and PD teams on performance, power, and area trade-offs
• Support sign-off flows and ensure timing, power, and reliability targets are met
• Contribute to physical design methodology and flow automation improvements
• Debug timing and physical design issues using industry-standard EDA tools
• Document best practices and provide guidance to cross-functional teams
• Participate in design reviews and provide timing expertise for new CPU features

Required Skills

• Static timing analysis (STA)
• Timing constraint development (SDC)
• ECO implementation for timing closure
• Place-and-route for advanced nodes
• Power, performance, area (PPA) optimization
• EDA tools: Prime
• Time, Tempus, Innovus, ICC2 or similar
• Scripting with TCL, Python or Perl
• Clock tree synthesis and optimization
• Signal integrity and noise analysis
• So
• C physical implementation flows